PERFORMANCE ENHANCEMENT COUNTER WITH MINIMAL CLOCK PERIOD

Performance Enhancement Counter with Minimal Clock Period

A synchronous binary counter is a fundamental component in VLSI design which are used hydrangea red sensation commonly.synchronous binary counter is fast and are used in many applications as it supports wide bit-width.Due to large fan-outs and long carry chains many previous counters have low counting rate when the size of the counters is large.A n

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Regulating of Passages in the Motorway Central Reserve

Passages in the central resetVes of mot01ways are intendedfor redirection of traffic during planned special maintenance ofmotorways and in accident situations, as well as for the requirementsof emergency vehicles (ambulance, fire-brigade, police).The observed problems in deficient legal regulations of thedesign and length of the passages are reflec

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